DK-DEV-5AGXB3N/ES【PDF 7/39 页】ARRIA V DEVELOPMENT KIT

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AV-51001

2013.12.26

Package Plan

7

Resource

A1

A3

A5

A7

Member Code

B1

B3

B5

B7

LVDS

Transmitter

Receiver

67

80

67

80

120

136

120

136

160

176

160

176

160

176

160

176

PCIe Hard IP Block

Hard Memory

1

2

1

2

2

4

2

4

2

4

2

4

2

4

2

4

Controller

Related Information

High-Speed Differential I/O Interfaces and DPA in Arria V Devices chapter, Arria V Device Handbook

Provides the number of LVDS channels in each device package.

Package Plan

Table 5: Package Plan for Arria V GX Devices

F672

F896

F1152

F1517

Member Code

(27 mm)

(31 mm)

(35 mm)

(40 mm)

GPIO

XCVR

GPIO

XCVR

GPIO

XCVR

GPIO

XCVR

A1

A3

A5

A7

B1

B3

B5

B7

336

336

336

336

—

—

—

—

9

9

9

9

—

—

—

—

416

416

384

384

384

384

—

—

9

9

18

18

18

18

—

—

—

—

544

544

544

544

544

544

—

—

24

24

24

24

24

24

—

—

—

—

704

704

704

704

—

—

—

—

24

24

36

36

Arria V GT

This section provides the available options, maximum resource counts, and package plan for the Arria V GT

devices.

The information in this section is correct at the time of publication. For the latest information and to get

more details, refer to the Altera Product Selector.

Related Information

Altera Product Selector

Provides the latest information about Altera products.

Arria V Device Overview

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